The present invention generally is directed to a multiple-level or particularly a 2-level metal BL-hierarchical structure for a hybrid NAND array termed as HiNAND2 array.
In conventional NAND array, the main memory organization and its associated DB (Data Buffer), SA (Sense Amplifier), CACHE Buffers Block-decoder, Row and Column decoders are much simpler but less flexibility. As a result, there are more latency and power consumption in all operations and usages. Fundamentally, the conventional NAND array is formed into a simple matrix that comprises 1-level BL structure that comprises a plurality of NAND blocks cascaded and connected by a plurality of long, tight-pitch (2λ), low-resistance metal1 bit lines (BLs) in parallel in column (y) direction and each block is further made of a plurality of NAND strings cascaded in row (x) direction. The inter-string gate connections in x-direction in a same block are easily made by a plurality of horizontal rows (or pages) using a tight-pitch (2λ) poly-gate word line (WL).
Typically, each conventional NAND String is made of M NAND cells that are connected in series with one top median-high voltage (MHV) NMOS select transistor and one bottom MHV NMOS select transistor, where M=8, 16, 32, 64, 128 or any arbitrary integer number. The connections of all NAND Strings in each column of a NAND array are made between a long tight-pitch 2λ metal BL and each N-active drain contact of each NAND string. For a conventional NAND array with 1-level BL scheme including an 8 KB physical page size in x-dimension and 64-cell physical string in y-dimension, there are totally 8 KB metal BLs in one physical page being divided into 4 KB odd-number metal1 BLs for an odd-half page and 4 KB even-number metal BLs for an even-half page with 64 common WLs. Every physical page includes two common string-select gate lines per one 8 KB block formed within a same Triple P-well (TPW) region within a same N-well region on top of a same P-substrate in one physical 2D NAND plane. Note, the 3D NAND may have different number of WLs per block in different P-substrate but have similar 1-level 3D metal BL structure.
In conventional NAND array, the SLC and MLC cells are physically placed in different blocks in either a same plane or different planes. So far, no SLC-page cells and MLC-page cells are physically placed within a single physical NAND block. As NAND manufacturing technology migrates toward extremely dense 10 nm class node, coupling effects of inter-WL and inter-BL cells become very severe to interfere the cell threshold level Vt. The degree of BL-BL and WL-WL coupling effects is almost same owing to the identical 1λ physical spacing. As a result, the NAND data quality and reliability are seriously degraded and require more sophisticated ECC algorithm and techniques applied on-chip or off-chip to correct the rising error bits. In the present application, BL-BL coupling effect will not be addressed here. This WL-WL coupling interfere effect is getting worse when all NAND cells of adjacent WLs within the same block are utilized to store same 4 MLC states. These WLs are referred as MLC-WL or MLC-page of the present application. The reason of worsen WL-WL interfering effect for a MLC-WL over a SLC-WL is because a 4-Vt MLC-WL cell has two more higher positive-Vt state cells, a B-state and a C-state, than a 2-Vt SLC cell which has only one lower positive-Vt A-state cell. The degree of coupling effect is proportional to the relative cell's Vt difference between any two adjacent cells physically residing on either different WLs but in same BL or different BLs but in same WL.
The higher MLC Vts of B-state and C-state store more electrons in a 2-poly floating-gate NAND cell or in a 1-poly charge-trapping Nitride NAND cell of the selected MLC-page, the more WL-WL coupling interfere effect will be than a SLC cell for storing at lower Vts of E-state and A-state. Thereby, it would result in the selected MLC cells with Vt levels of E-state, A-state, and even B-state being increased more by two MLC's C-state cells from two physically adjacent, top and bottom, MLC-WLs than SLC cells with E-state being increased by two adjacent SLC's B-state cells from two physically adjacent SLC-WLs.
Conventionally, the NAND memory is formed entirely separated as either a MLC NAND or a SLC NAND in separate chip. But due to new NAND application need recently, a hybrid NAND design containing both types of MLC and SLC storages in one die is required. When it comes to a hybrid MLC and SLC NAND design, reliable maintaining both data quality and integrity of SLC and MLC of NAND array in one chip is a big concern. There are many ways to construct this hybrid NAND array in prior art. One example, each physically separate plane of a hybrid NAND array to respectively acts as a big unit to store SLC-only data or MLC-only data. This can be referred as a plane-based hybrid NAND array.
Another example, each physically separate Block of a hybrid NAND plane to respectively acts as a medium unit to store SLC-only data or MLC-only data. This can be referred as a block-based hybrid NAND array. The block that stores SLC data is referred as SLC-block, while the block that stores MLC data is referred as MLC-block.
For above conventional SLC-block, the WL-WL coupling effects from two adjacent WLs is less severe, thus the cell data quality and integrity of each SLC-block can be reliably maintained. By contrast, the cell quality of each MLC-block is greatly degraded due to much more severe WL-WL coupling effect when the technology migrates to below 20 nm node.
As a result, a conventional hybrid NAND memory inherently provides improved quality of SLC data along with a degraded MLC data, however, MLC data is prone to be corrupted so that a more sophisticated ECC method is required to correct those MLC errors when it happens.
Additionally, the conventional NAND Erase scheme is performed in a unit of a physical block. In other words, all physical WLs' NAND cells in one physical NAND block are getting erased collectively and concurrently. So far, a page-based Erase operation is not allowed, not mentioning a random page-erase operation. This is a tremendous inconvenience of updating file system if only a small size of page change is required. As a result, many unnecessary big-block erase and a plurality of small page programs are disadvantageously performed so that NAND P/E endurance cycles are greatly reduced for both SLC, MLC, TLC and even XLC NAND, regardless of 2D or 3D NAND, or regardless of 2-poly floating-gate NAND or 1-poly charge-trapping Nitride NAND, regardless of PMOS NAND or NMOS NAND.
Typically, the state-of-art 2D NAND cell's Erase operation is performed by using a FN-channel tunneling scheme to decrease cell's Vts from all high programmed positive-Vt states to a low negative-Vt state, regardless of SLC, MLC, TLC, XLC and even Analog storages. As defined in a conventional NAND cell Vt distribution diagram, commonly there is only one negative-Vt state (Vte≦−0.5V) which is termed as E-state with data being set to “1” for all storage types. Similarly, NAND program operation also uses same FN-channel tunneling scheme to increase cell's Vt to multiple higher positive values. The number of the positive values of multiple programmed Vt states is determined by NAND cell's preferred storage type. For example, a SLC-type NAND cell has only one positive programmed Vt state which is referred as A-state with a center value of Vta set to be around 1.0V. For a MLC-type NAND cell, it has three positive programmed states conventionally termed as A-state, B-state, and C-state with a respective Vt center value set as Vta=1.0V, Vtb=2.0V, and Vtc=3.0V. Similarly, a TLC cell has seven positive programmed states, a XLC cell has fifteen positive programmed states and a Analog NAND cell can have up to 255 positive programmed states but with a much narrowly-spaced Vt spacing between any two adjacent programmed states. Typically, a Vt spacing, ΔVt1, between the negative erased state of Vte and next positive programmed state of Vta is much larger than other Vt spacing, ΔVts, between any two higher positive programmed Vt states such as ΔVt2=Vtb−Vta, ΔVt3=Vtc−Vtb, etc. In NAND design with more multiple positive programmed states, it has smaller ΔVt in a nLC NAND cell. As a result, nLC is more prone to data corruption, when n>1 (for MLC, XLC, TLC, etc.).
When performing a page-program operation on a selected page of a state-of-art NAND product, a pre-erase-before-program is required. The first step is to follow a block-erase command to carry out a block-based Erase operation. After a long time of about 2-5 ms erase time, all NANDs' Vts in a selected block that contains the selected page are reset to E-state with Vte below 0V. Even a typical NAND block comprising N physical pages of WLs (N=16, 32, 64, or 128) only needs to change one single page (WL) data, the whole block has to be erased to allow one or even partial WL program.
The final required erase time is heavily depending on NAND cell's storage type, block size, technology node of 2D or 3D NAND flash. Although program time, program gate voltages, and Program-Verify conditions vary with Vt and the storage types of SLC, MLC, TLC, XLC or Analog, the erase time remains the pretty much identical because so far the NAND cell has only one erased state with one erased Vt=Vte. During an Erase operation, the TPW of the selected NAND plane of NAND array has to be coupled with a HV of +20V along with the multiple WLs in one selected erased block coupled to 0V to induce the desired FN-channel tunneling effect to remove the stored electrons out from the floating-gate of 2-poly NAND cells or the Nitride charge-trapping layer in 1-poly SONOS or MONOS NAND cells.
For those cells in the unselected WLs and in the unselected blocks are left in a floating state initially so that when the subsequent voltage rise of the selected TPW to 20V for Erase operation, the unselected floating WLs' voltage would also be coupled up to near 20V so that the voltage drop between the unselected WLs and common TPW would be small. As a result, no FN-tunneling effect would be induced. Thus, the NAND cells' Vts in the unselected blocks in both selected or unselected NAND plane would remain unchanged with a negligible ΔVt.
Since the NAND erase size in spec is performed in unit of Block, but the NAND program size is performed in unit of single page, thus there are many disadvantages in above said Erase-before-Program step, as listed below.                1) Erase-before-Program step reduces NAND's limited P/E endurance cycles:                    Any one page or partial Program operation of NAND requires a Block-erase to reset all NANDs' Vts to Vte of all pages in one selected Block. Even there is only one page to be programmed with a new data, the rest of M−1 WLs in the selected Block need to be reprogrammed back with the old data in the selected erased Block. Therefore an operation of any single page data change in a selected Block, cells in each of M−1 pages suffer unnecessary one erase 20V TPW stress and M−1 page program 20V WL voltage stresses, thus NAND's P/E endurance cycles would be degraded and reduced per each new data change.                        2) Erase-before-Program step drastically shorten NAND's life cycle:                    In the state-of-art 2D or 3D NAND spec, the Block-erase time is set to be ˜2.5 ms per block. But SLC program time spec is set to be 250 ms. Thus each Block-erase time is about 10-fold of each page-program time. Thus, the lengthy Erase-before-Program operation rather than page-program operation is the speed bottleneck to change NAND data.                        3) Block-erase step results in more power consumption than unnecessary page-program:                    In the pre-erase step, a 20V HV has to be coupled to the selected TPW in selected NAND plane. Typically, a whole big NAND array is only being divided into 2 or 4 or 8 planes. Thus even only one NAND plane is selected for Erase, the 20V HV requirement in the selected NAND plane is still consuming huge power because the area of the selected TPW area is still a big parasitic capacitor that needs to be filled up with a 20V by An Erase pump circuit. Although the Block-erase time seems to be same as page-erase, the unnecessary extra program time and power consumption for M−1 pages slows down and degrades overall operation.                        
Since it is impractical to physically separate the common TPW between any adjacent WLs or BLs without a big penalty in NAND array layout area, the conventional NAND spec only allows the Erase operation to be conducted on a block-based manner, rather than on a page-based manner as the page-program operation.
Conversely, NAND Program operation only applies Vpgm of 20V to a selected WL and Vpass (of 10V) to the remaining M−1 WLs of the selected Block with TPW coupled to Vss. Thus in NAND Program operation, no big TPW disturbance exists at the unselected pages (WLs) and Blocks. Thereby, the NAND Program is performed on page-based manner with a page-program time of approximate 250 μs for a SLC cell as only one programmed A-state is required. For a MLC cell a 3-fold program time of 750 μs is required as three programmed states of A-state, B-state, and C-state are required. Further, the page-program time is proportionally increased even more when programming a TLC-type cell and a XLC-type cell or an Analog cell. Practically, Erase operations in prior art NAND can be randomly and independently executed on single page base. But in reality, due to above said program sequence drawback, typical NAND Erase spec only allows the block-based Erase, no random page-based Erase is allowed.
Moreover, even the spec of Program operation is allowed to be performed in unit of page, the sequence of page-program WL in the selected Block has a stringent restriction. The sequence of NAND's page-program in the erased Block has to start from the first WL nearing the bottom of NAND Strings to the last WL nearing the top of NAND Strings. Usually, the Block size comprises 64 WLs, although other numbers like 32 or 128 physical pages or WLs are also used. The page-program sequence starts from WL0, then WL1, then to last WL63 in a 64-cell NAND strings. A random WL program is prohibited in the conventional NAND array, regardless of SLC or MLC and 2D or 3D type of cells.
One conspicuous reason to prohibit the conventional NAND from providing random page program scheme is because the limitation of all self-boost (SB) Program-Inhibit schemes, regardless of SB, ESB and LSB techniques. A successful random page program operation requires a SB program-inhibit scheme to well boost the channel's initial inhibited voltage of Vdd or Vdd-Vt to more than 7.0V when a selected WL is coupled with a rising Vpgm=20V and the rest of N−1 unselected WLs in the selected block are coupled with a rising Vpass=10V. In a random-page program scenario, it means the unselected N−1 NAND cells in WLn+1 or WLn−1, above or below the selected WLn, may be in the programmed states with Vta, Vtb, and Vtc which are higher than Vte (a negative Vt) state. Then the Vpass coupling from gates of non-selected WLs to channels of non-selected cells would be drastically reduced to 3V. As a consequence, the selected WL coupling of 20V would not be strong enough to boost the channel of selected cell above 7V due to its leakage to the adjacent under-boosted channels of unselected cells in the same NAND string. Thus the program operation may fail and the situation becomes worse if the cells in a same selected WL but in two adjacent BLs are in program state with channel voltage at Vss because the boosted WL voltage of 20V has to boost higher BL voltage coupling BL parasitic capacitance.
But if the program sequence starts from NAND bottom with the unprogrammed NAND cells' Vt in WLn+1 to top WL being still in Vte states, that would maintain a high Vpass coupling ratio to assist Vpgm boosting on the channel of selected cell so that a higher success rate in program-inhibit operation.
For the reasons stated above and strong market demands, it is desirable to provide advanced NAND products for supporting random-page operation along with the page-based Erase operation to avoid the unnecessary Erase and Program operations to those unselected pages or WLs. It is desirable to have new hybrid NAND memory technique to improve MLC data quality. Further it is desired to achieve a faster write operation with a higher P/E endurance cycle and superior NAND data integrity and reliability for a low-current NAND regardless of 2D or 3D NAND, or 1-poly charge-trapping Nitride SONOS or MONOS NAND, or 2-poly floating-gate type NAND for either PMOS or NMOS NAND.